Various semiconductor, circuit, and integrated circuit (“IC”) devices, such as system-on-chip (“SoC”) devices, are emulated or verified during their design and development processes. As an example, highly-integrated SoC devices may power or support a wide variety of products to facilitate various hardware, software, and/or device applications. To meet these demands, SoC devices continue to increase in size and complexity, and their capabilities and manufacturability are in part aided by advance semiconductor processing technologies and availability of verified and well-developed libraries, e.g. design or circuit intellectual property (“IP”) libraries. The development of SoCs or other circuits or devices in some cases nevertheless may increase the burden on design verification processes, methods, or systems. In some cases, verification may consume a significant amount of time or resources during an SoC development cycle.
Circuit design verification approaches can vary. Given the expectation for speed, the various approaches of software development, hardware development, or system validation may provide varying levels of observability and control. Field programmable gate array (“FPGA”) prototype systems, for example, can provide improved system execution time due to its hardware-based implementation. Some FPGA verification systems, nevertheless, lack the ability to isolate some of the root causes of discoverable errors for various reasons. For example, the lack of visibility regarding the multitude of signals within the design. Depending on the environment, software, and hardware constraints, in some cases, deficiencies in certain FPGA vendor-specific verification tools may include access to a limited number of signals, and limited sample capture depth. Even combined with an external logic analyzer, FPGA vendor-specific verification tools, in some instances, may lack sufficient capabilities to isolate root cause errors during design verification.
Functional qualification is a technology that provides an objective answer to the question of whether there is a bug or other defect in the design of an integrated circuit. Functional qualification has become an important addition to solutions available for the increasingly challenging task of delivering functionally correct silicon on time and on budget. Functional qualification enables the rapid improvement and cost reduction of verification.
To be effective, verification must ensure that designs are shipped without critical bugs. To find a design bug, at least three things must occur during the execution of the verification environment. First, the bug must be activated. In other words, the code containing the bug must actually be exercised. Second, the bug must be propagated to an observable point (e.g., to the outputs of the design). Third, the bug must be detected (i.e. behavior is checked and a failure indicated).
Traditional electronic design automation (EDA) technologies have focused on the first aspect, activating the bug. Techniques such as code coverage and functional coverage can help ensure that design code is well-activated. However, these techniques do not guarantee that design bugs will be propagated to an observable point. Nor can they guarantee that the bugs will be detected by any checkers, assertions, or comparison against a reference model.
Functional qualification automatically inserts artificial bugs into the design and determines if the verification environment can detect these bugs. A known artificial bug that cannot be detected points to a verification weakness. If an artificial bug cannot be detected, there may be evidence that actual design bugs would also not be detected by the verification environment. Functional qualification tools help users understand the nature of these verification weaknesses thus providing new information to the verification engineer (verifier).
When designs are increasingly complex, functional qualification becomes more difficult for designers. In general, simulation-based verification methods are the mainstream in the current design flow, especially for large designs. Due to the fact that exhaustive simulation is infeasible, metrics can be used measure the quality of verification and thus reduce the simulation cost. However, the completeness problem still remains in that even with a reduced simulation cost, such simulations are still a limiting factor in the verification process.
Accordingly, what is desired is to solve problems relating to functional qualification, some of which may be discussed herein. Additionally, what is desired is to reduce drawbacks relating to functional qualification, some of which may be discussed herein.